One form of a peak detector is a circuit that senses the amplitude of a time varying signal and provides a logic one output if the amplitude is greater than a predetermined value and a logic zero output if the amplitude is less than the predetermined value. One common implementation of the peak detector comprises an amplifier with feedback and an integrator. Various sources for error are associated with the amplifier and noise can be introduced into different parts of the circuit. Offset error compensation is used to reduce some of the effects of the error. However, in some applications the peak detector will not function reliably because the signal level is smaller than the potential offsets and errors in the amplifier. Also, the integrator can introduce error and/or uncertainty in the logic output.
Therefore, it is desirable to provide a peak detector circuit that can convert small signal levels and compensate for error.